Crusoe Processors: The Hybrid Approach

2 April, 2000.

The Crusoe processor consists of a hardware engine logically surrounded by a software layer, named Code Morphing software. The CPU is a very long instruction word (VLIW) CPU that executes up to four operations in each clock cycle. The native instruction set has been designed purely for fast low-power implementation; it bears no resemblance to the x86 instruction set. The surrounding software layer gives x86 software the impression that they are running on x86 hardware.

Some functions have been rendered in hardware and some in software, and this philosophy changes the entire approach to microprocessor design. Upgrades to the software portion of a microprocessor can be delivered independently from the chip itself. Decoupling the hardware design from the system and application software that use it, frees hardware designers to evolve and eventually replace their designs without disturbing legacy software. Because the Code Morphing software would typically reside in standard Flash ROMs on the motherboard, improved versions can even be downloaded into processors in the field. (For better performance, the Code Morphing software copies itself from ROM to DRAM at initialization time.)

The VLIW (Very Long Instruction Word) CPU:

The CPU VLIW Engine incorporates two integer units, a floating-point unit, a memory (load/store) unit, and a branch unit. A Crusoe processor long instruction word, called a molecule, can be 64 bits or 128 bits long and contain up to four RISC-like instructions, called atoms. All atoms within a molecule are executed in parallel, and the molecule format directly determines how atoms get routed to functional units; this greatly simplifies the decode and dispatch hardware. Molecules are executed in order, so there is no complex out-of-order hardware. To keep the processor running at full speed, molecules are packed as fully as possible with atoms. The integer register file has 64 registers, %r0 through %r63, out of which some are allocated to hold x86 state while others contain state internal to the system, or can be used as temporary registers.

In addition, Crusoe processors provide upto 128 KB of on-chip L1 cache, and upto 256 KB of on-chip L2 cache. Crusoe requires no active cooling, yet can play a DVD at a temperature not more than 48 ∫C ! (Compare this with the astoundingly high 105.5 ∫C of the Pentium III Processor for the same performance, and youíll realize the difference!).

The Code Morphing software:

The Code Morphing software is a dynamic translation system, a program that compiles instructions for x86 target instruction set architecture (x86 ISA) into instructions for VLIW host ISA at runtime. The Code Morphing software resides in a ROM and is the first program to start executing when the processor boots. It translates an entire group of x86 instructions at once, creating an optimized translation, (whereas a superscalar x86 translates single instructions in isolation). Moreover, while a traditional x86 translates each instruction every time it is executed, on a Crusoe, instructions are translated once, and the resulting translation is saved in a translation cache, making use of Locality of Reference property of code. The next time the (already translated) x86 code is executed, the system skips the translation step and directly executes the existing optimized translation. Not every piece of code is translated in the same manner: there is a wide choice of execution modes for x86 code, ranging from interpretation (which has no translation overhead at all, but executes x86 code more slowly), through translation using very simple-minded code generation, all the way to highly optimized code (which takes longest to generate, but which runs fastest once translated). Dynamic feedback information gathered during actual execution of the code optimizes this process. Crusoe hardware, in comparison with other x86 processors, can achieve excellent performance in dynamic translation, because it has been specifically designed with dynamic translation in mind.

The flexibility of the software-translation approach comes at a price: the processor has to dedicate some of its cycles to running the Code Morphing software; cycles that a conventional x86 processor could use to execute application code. However, the advantages of such an approach far outweigh its limitations.

LongRun™ Power Management:

LongRun Power Management is a facility in the TM5400 model Crusoe that can further minimize that processorís already low power consumption. In a mobile setting, most conventional x86 CPUs regulate their power consumption by rapidly alternating between running the processor at full speed and turning the processor off. However, the processor may be shut off just when a time-critical application needs it. In contrast, the TM5400 can adjust its power consumption without turning itself off - instead, it adjusts its clock frequency on the fly, without even requiring an operating system reboot. As a result, software can continuously monitor the demands on the processor and dynamically pick just the perfect clock speed (and hence power consumption) needed to run the application.

The significance of the hybrid approach to microprocessor design is likely to become more apparent over the next several years. The technology offers more freedom to innovate (both hardware and software) than conventional hardware-only designs. Nor is the approach limited to low-power designs or to x86-compatible processors. Initially targeted at the mobile computing market, Crusoe processors can give devices such as mobile computers and Internet access devices, PC capabilities and unplugged running times of up to a day.